The present invention relates to a semiconductor design technology, and more particularly to a power up signal generation circuit and a method for generating a power up signal.
In general, semiconductor devices such as a double data rate synchronous DRAM (DDR SDRAM) include a power up signal generation circuit for ensuring a stable operation of an internal circuit. The power up signal generation circuit determines whether an external power supply voltage applied from the outside has a sufficient voltage level for a stable operation of an internal circuit to output it as a power up signal.
The semiconductor devices include various internal circuits for performing a variety of operations. The various internal circuits include PMOS transistors and NMOS transistors, particularly, PMOS transistors and NMOS transistors for receiving an internal power supply voltage as a bias voltage. The internal power supply voltage is generated by dividing or boosting the external power supply voltage, and thus has a voltage level corresponding to the external power supply voltage. Accordingly, if the PMOS transistors and the NMOS transistors, which receive the internal power supply voltage as a bias voltage, are operated while the external power supply voltage still has insufficient voltage level, problems such as latch up may be caused, which may be a cause of severe damages to a semiconductor device. To prevent such problems, the semiconductor device utilizes the power up signal.
In general, the power up signal maintains a ground voltage until the external power supply voltage is increased to a target voltage level, and is transited to the external power supply voltage when the external power supply voltage has a target voltage level. While the power up signal maintains the ground voltage, the semiconductor device performs an initialization and a stabilization.
The target voltage level depends on a design, and is recently being designed to have a hysteresis characteristic. That is, the target voltage level is designed to secure stable operations of the internal circuits in a period where the external power supply voltage is increased to power on the semiconductor device. The target voltage level is also designed to prevent the reset of the power up signal due to a voltage drop of the external power supply voltage caused by a power consumption or a power noise in a period where the external power supply voltage is decreased to power off the semiconductor device. In other words, the target voltage is designed differently in a rising period of the external power supply voltage and in a falling period of the external power supply voltage.
FIG. 1 is a circuit diagram of a conventional power up signal generation circuit.
Referring to FIG. 1, the power up signal generation circuit includes a voltage division unit 110, a voltage detection unit 130 and a power up signal drive unit 150.
The voltage division unit 110 is configured to divide the external power supply voltage to generate a divided voltage V_DIV. To do this, the voltage division unit 110 includes a first resistor R11 and a second resistor R12, which are serially connected between an external power supply voltage terminal VDD and a ground voltage terminal VSS. The divided voltage V_DIV varies linearly with the external power supply voltage.
The voltage detection unit 130 is configured to receive the divided voltage V_DIV to output a target voltage level as a voltage detection signal V_DET. To do this, the voltage detection unit 130 includes a third resistor R13 and a first NMOS transistor NM11 which are serially connected between the external power supply voltage terminal VDD and the ground voltage terminal VSS. The voltage level of the voltage detection signal V_DET is an important factor in determining the time when a power up signal PWRUP is transited to the external power supply voltage.
The power up signal drive unit 150 includes an inverter INV11 and a second NMOS transistor NM12 to generate the power up signal PWRUP in response to a voltage detection signal V_DET. The inverter INV11 buffers the voltage detection signal V_DET to output the power up signal PWRUP, and the second NMOS transistor NM12 drives an input terminal of the inverter INV1 in response to the power up signal PWRUP. Here, the second NMOS transistor NM12 allows the power up signal has a different target voltage level in the falling period of the external power supply voltage from that in the rising period of the external power supply voltage. This will be described in detail below.
FIG. 2 is an operation-timing diagram illustrating voltage levels of the external power supply voltage terminal VDD and the power up signal PWRUP of FIG. 1. In FIG. 2, the horizontal axis represents a time, and the vertical axis represents a corresponding voltage. For convenience of explanation, the target voltage level in the rising period of the external power supply voltage is referred to as a ‘first target voltage level’ and represented by a reference numeral ‘V1’. In addition, the target voltage level in the falling period of the external power supply voltage is referred to as a ‘second target voltage level’ and represented by a reference numeral ‘V2’.
Referring to FIGS. 1 and 2, in a period before t1, the external power supply voltage is increased gradually, which is applied to power on the semiconductor device. However, because the first NMOS transistor NM11 is still turned off, the voltage detection signal V_DET has a voltage level corresponding to the external power supply voltage. Hence, the power up signal PWRUP maintains the voltage level of the ground voltage terminal VSS.
In a period from t1 to t2, the external power supply voltage continues to be increased gradually, so that the drive current of the first NMOS transistor NM11 is also increased gradually. As the external power supply voltage reaches the first target voltage level V1, the first NMOS transistor NM11 is turned on so that the voltage detection signal V_DET has the voltage level of the ground voltage terminal VSS. As a result, the power up signal PWRUP is transited to the external power supply voltage in response to the voltage detection signal V_DET. Here, the second NMOS transistor NM12 is turned on in response to the power up signal PWRUP.
In a period from t2 to t3, the external power supply voltage maintains a sufficient voltage level, and thus the power up signal PWRUP also maintains a voltage level proportional to the external power supply voltage. Here, the external power supply voltage may experience a voltage drop due to power consumption or power noise. If the external power supply voltage is dropped below the first target voltage level V1, the first NMOS transistor NM11 may be turned off. However, as the second NMOS transistor NM12 still maintains the turn on state by receiving the fed back power up signal PWRUP, the power up signal PWRUP is not transited to the voltage level of the ground voltage terminal VSS. That is, the power up signal PWRUP is not reset.
In a period from t3 to t4, the external power supply voltage is decreased to power down the semiconductor device. When the external power supply voltage is higher than the second target voltage level V2, although the first NMOS transistor NM11 is turned off, the power up signal PWRUP is not reset because the second NMOS transistor NM12 still maintains the turn on state, as described above. Afterwards, as the external power supply voltage is decreased below the second target voltage level V2, the second NMOS transistor NM12 is turned off, and thus, the power up signal PWRUP is transited to the voltage level of the ground voltage terminal VSS.
In summary, the first target voltage level V1 in the rising period of the external power voltage is determined by the ratio of the resistance of the third resistor R13 to the turn on resistance of the first NMOS transistor NM11. On the contrary, the second target voltage level V2 in the falling period of the external power supply voltage is determined, as the first NMOS transistor NM11 is turned off, by the ratio of the resistance of the third resistor R13 to the turn on resistance of the second NMOS transistor NM12.
That is, the second target voltage level V2 is determined by the design of the third resistor R13 and the second NMOS transistor NM12. However, in the conventional power up signal generation circuit, the second target voltage level V2 is variable for the following reasons.
The conventional power up signal generation circuit determines the second target voltage level V2 depending on the second NMOS transistor NM12. That is, the conventional power up signal generation circuit has a feedback configuration where the power up signal PWRUP is generated according to the voltage detection signal V_DET, the second NMOS transistor NM12 is controlled by the power up signal PWRUP, and the voltage level of the voltage detection signal V_DET is determined by the second NMOS transistor NM12 and the third resistor R13. Therefore, the second target voltage level V2 depends on the design of the second NMOS transistor NM12.
However, the properties of the second NMOS transistor NM12 are varied with conditions of a process, a voltage, and a temperature. Hence, the second target voltage level V2 is also varied with the conditions of the process, the voltage, and the temperature. The second voltage level V2 varying differently from the predetermined voltage level may enlarge the variation of the power up signal PWRUP.
Hereinafter, the effect of the enlarged variation of the power up signal PWRUP will be described.
Referring back to FIG. 2, in a period A where the second target voltage level V2 is higher than the predetermined voltage level (a voltage level at t4), the power up signal PWRUP may be reset unexpectedly by a voltage drop of the external power supply voltage, which is caused by a power consumption or a power noise.
In a period B where the second target voltage level V2 is lower than the predetermined voltage level, if the semiconductor device is powered on quickly after being powered off, the power up signal PWRUP may maintain the external power supply voltage without the reset period where the power up signal PWRUP has the voltage level of the ground voltage terminal VSS. That is, although the external power supply voltage is lowered below the predetermined voltage level by the power off operation, the power up signal PWRUP is not reset, and before being transited to the voltage level of the ground voltage terminal VSS, the power up signal PWRUP is raised again according to the external power supply voltage by the power on operation. This may result in that the internal circuit cannot detect the power off operation and thus the semiconductor device cannot perform the initialization. This may cause malfunctions of the semiconductor device.